68 Programmable Logic Devices (PLD) 9

Reset All

Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Maximum Time At Peak Reflow Temperature (s)	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
ISPLSI1024-60LJI	Lattice Semiconductor	EE PLD	Industrial	No Lead	68	QCCJ	Square	Plastic/Epoxy	25 ns	Yes	5.5 V	96	CMOS	5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 48 I/O	2	-40 °C (-40 °F)	Tin/Lead (Sn85Pb15)	Quad	S-PQCC-N68	3	4.57 mm	24.2316 mm	No	In-System Programmable; 4 External Clocks	e0	38 MHz	30 s	225 °C (437 °F)	24.2316 mm	No	48
ISPLSI1024-60LJ	Lattice Semiconductor	EE PLD	Commercial	No Lead	68	QCCJ	Square	Plastic/Epoxy	25 ns	Yes	5.25 V	96	CMOS	5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 48 I/O	2	0 °C (32 °F)	Tin/Lead (Sn85Pb15)	Quad	S-PQCC-N68	3	4.57 mm	24.2316 mm	No	In-System Programmable; 4 External Clocks	e0	38 MHz	30 s	225 °C (437 °F)	24.2316 mm	No	48
EPM7096LC68-10	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns	Yes	5.25 V	96	CMOS	5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	3	5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz		220 °C (428 °F)	24.2316 mm	No	52
EPM7096LC68-12	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	12 ns	Yes	5.25 V	96	CMOS	5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	3	5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz		220 °C (428 °F)	24.2316 mm	No	52
EPM7096LC68-15	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns	Yes	5.25 V	96	CMOS	5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	3	5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	100 MHz		220 °C (428 °F)	24.2316 mm	No	52
EPM7096LC68-7	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	7.5 ns	Yes	5.25 V	96	CMOS	5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	3	5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	166.7 MHz		220 °C (428 °F)	24.2316 mm	No	52
EPM7096LI68-15	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns	Yes	5.5 V	96	CMOS	5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 52 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68	3	5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	100 MHz		220 °C (428 °F)	24.2316 mm	No	52
ATF1504AS-10JC68	Atmel	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns	Yes	5.25 V	64	CMOS	5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 48 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	3	4.57 mm	24.2316 mm	No	64 Macrocells; In-system programmable; JTAG boundry-scan test circuitry	e0	125 MHz		225 °C (437 °F)	24.2316 mm	Yes	48
EP1800ILC-70	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic	70 ns	Yes		48	CMOS	5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0			220 °C (428 °F)		No

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.